Look-up engine for packet-based network

ABSTRACT

An arrangement is disclosed for parsing packets in a packet-based data transmission network. The packets include packet headers divided into fields having values representing information pertaining to the packet. The arrangement includes an input receiving fields from the packet headers of incoming packets, a memory for storing information related to possible values of said fields, and a device for retrieving the stored information appropriate to a received field value. The retrieving device comprises a look-up engine including at least one memory organized in a hierarchical tree structure, and a controller for controlling the operation of the memory. The arrangement is capable of performing fast look-up operations at a low cost of implementation.

BACKGROUND OF THE INVENTION FIELD OF THE INVENTION

This invention relates to the field of data communications, and moreparticularly to packet-based digital communications networks.

There are two broad classes of network: circuit-based and packet-based.Conventional telephone networks are circuit based. When a call isestablished in a circuit-based network, a hard-wired connection is setup between the calling parties and remains in place for the duration ofthe call. Circuit-based networks are wasteful of available bandwidth andlack flexibility.

Packet-based networks overcome many of the disadvantages ofcircuit-based networks. In a packet-based network, the data areassembled into packets containing one or more address fields whichdefine the context of a packet, such as protocol type and relativepositions of other fields embedded in the packet. LAN bridges androuters use the information in the packet to forward it to thedestination.

In a packet-based network, a packet must be parsed as it flows throughthe network. Parsing is the process of extracting and analyzing theinformation, such as source and destination address and net layerprotocol, contained in the packets.

In known networks, packet parsing is generally performed with amicroprocessor, which provides flexibility in handling different packettypes and can be upgraded to handle new packet types as they aredefined. Content Addressable Memory (CAM) is commonly used for hardwareassistance to speed up searches through a list of known addresses. Thisis a tedious task. CAMs are also relatively expensive and limited insize and availability.

General purpose processor architectures are not specifically directedtoward the types of operations required in packet parsing and so theytend to be inefficient. To meet performance requirements, a fast butexpensive processor based solution can be implemented. In the highestperformance systems, hardware solutions are implemented to increasespeed, but at the cost of flexibility.

SUMMARY OF THE INVENTION

An object of the invention is to provide a fast, but inexpensivesolution to the problem of packet-parsing in packet-based networks.

According to the present invention there is provided an arrangement forparsing packets in a packet-based digital communications network, saidpackets including packet headers divided into fields having valuesrepresenting information pertaining to the packet, said arrangementcomprising an input memory for receiving fields from said packet headersof incoming packets; and a look-up engine for retrieving storedinformation appropriate to a received field value. The look-up engineincludes at least one memory storing information related to possiblevalues of said fields in a hierarchical tree structure and associatedwith a respective field of packet headers; a memory controllerassociated with each said memory storing information related to possiblevalues of said fields for controlling the operation thereof to retrievesaid stored information therefrom; and a microcode controller forparsing a remaining portion of the packet header while said storedinformation is retrieved and controlling the overall operation of saidlook-up engine.

The memory and retrieving means constitute a look-up engine, which isthe central resource containing all information necessary for forwardingdecisions. In a preferred embodiment the look-up engine includes asource address look-up engine and a destination address look-up engine.

In a packetized data transmission conforming to IEEE802 standards, thepackets have a MAC (medium access control) header containing informationabout the destination and source addresses and the net layer protocol.The invention permits packet switching to be achieved in abridge-router, for example an Ethernet to ATM bridge-router, at a rateof about 178,000 packets per second using 64 byte minimum Ethernetpackets. This means that the MAC headers are interpreted once every 5.6micro seconds.

The look-up engine preferably employs table look-ups using nibbleindexing on variable portions of the packet, such as MAC and networklayer addresses, and bit pattern recognition on fixed portions fornetwork layer protocol determination.

Each look-up table is organized into a hexadecimal search tree. Eachsearch tree begins with a 16 word root table. The search key (e.g. MACaddress) is divided into nibbles which are used as indices to subsequenttables. The 16 bit entry in the table is concatenated with the next 4bit nibble to form the 20 bit address of the next 16 word table. Thefinal leaf entries point to the desired information.

Bit pattern recognition is achieved by a microcode instruction set. Themicrocode engine has the ability to compare fields in a packet topreprogrammed constants and perform branches and index increments in asingle instruction cycle typically. The microcode engine has completecontrol over the search procedure, so it can be tailored to specificlook-up functions. New microcode is downloaded as new functions arerequired.

The look-up engine can perform up to two tree searches in parallel withmicrocode execution. Look-up time is quick because the microcodedetermines the packet's network layer format while the source anddestination addresses are being searched in parallel. The results of thesource and destination look-ups and the protocol determination arrive atroughly the same time, at which point the next level of decisions ismade.

The look-up engine also performs protocol filtering between areas. Thesystem allows devices to be grouped arbitrarily into areas on a perprotocol basis and defines filtering rules among these areas. Thelook-up engine keeps track of each station's area for each of itsprotocols. The source and destination areas are cross-indexed in asearch tree, which is used to find the filtering rule between the twoareas. Separate filtering rules are defined for bridging and networklayer forwarding; bridging is normally allowed within an area whilenetwork layer forwarding is selectively allowed between areas.

The parsing controller typically has a pointer to the current field inthe packet being examined. The controller moves this pointer to the nextfield in the packet after all decisions based on the current field aremade.

At each decision point on a tree, the current field is compared to aknown value or range. If the comparison yields a true condition, thecontroller moves to the next decision point by moving the current fieldpointer. Otherwise the field pointer is left alone and controllerbranches to new code to compare the current field to a different valueor range. This process is repeated until a final decision is made.

Moving to the next decision point requires several discrete steps in ageneral purpose processor. Unlike a general purpose processor, which hasthe disadvantage that it only has a single memory bus for bothinstruction and data fetches, the Look-up engine controller has separatebuses for instruction and data and typically performs one decision perstep. Fast decisions are made possible by a special set of instructionswhich both conditionally move the pointer and conditionally branch tonew code in a single step. The comparisons and pointer movements can bebyte or word wide, according to the current field's size.

The look-up engine implements other optimized instructions which performbit level logical comparisons and conditional branches within the samecycle as well as other instructions tailored to retrieving data fromnibble-indexed data structures.

The look-up engine is preferably divided into the following sections:

a) one or more nibble tree address look-up engines (ALE)

b) one microcode engine

Each ALE is used to search for addresses in a tree structure in its ownlarge bank of memory. The result of a search is a pointer to pertinentinformation about the address. An ALE is assigned to destinationaddresses (DALE) and source addresses (SALE). The ALEs operateindependently of each other.

The microcode engine is used to coordinate the search. It invokes theSALE and DALE to search for the source and destination addressesrespectively and continues on to parse the remainder of the packet usingan application-specific instruction set to determine the protocol.

The SALE, DALE and microcode engine can execute in parallel and arriveat their corresponding results at roughly the same time. The microcodeengine then uses the SALE and DALE results along with its own to arriveat the forwarding decision.

The advantage of using RAM over a CAM is expandability and cost.Increasing RAM is a trivial and inexpensive task compared to increasingCAM size.

The advantage of the microcode engine over a general purpose processoris that an ASIC implementation of the function is much less expensiveand less complex than a processor-based design with all the overhead(RAM, ROM) associated with it.

The invention also related to a method of parsing packets in apacket-based data transmission network, said packets including packetheaders divided into fields having values representing informationpertaining to the packet, comprising storing information related topossible values of said fields, receiving fields from said packetheaders of incoming packets, and retrieving said stored informationappropriate to a received field value, characterized in that saidinformation is stored in a memory organized in a hierarchical treestructure.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will now be described in more detail, by way of exampleonly, with reference to the accompanying drawings, in which:

FIG. 1 is an example of a MAC layer header of a typical packet;

FIG. 2 shows the data paths in a typical bridge-router between EthernetLAN and ATM networks;

FIG. 3 is a block diagram of a first embodiment of a look-up engine inaccordance with the invention;

FIG. 4 is a block diagram of a look-up engine controller for the look-upengine shown in FIG. 3;

FIG. 5 is a block diagram of a second embodiment of a look-up engine inaccordance with the invention;

FIG. 6 is a block diagram of a look-up engine controller for the look-upengine shown in FIG. 5;

FIG. 7 is a map of look-up engine Address Look-up engine (ALE) memories;

FIG. 8 is a diagram illustrating search tree operation in an ALE;

FIG. 9 shows one example of a MAC search tree;

FIG. 10 shows the effect of the organizationally unique identifier ofthe MAC addresses on the size of the search tree;

FIG. 11 shows the source address look-up engine table;

FIG. 12 shows the destination address look-up table;

FIG. 13 illustrates the look-up engine addressing modes;

FIG. 14 shows a station information block;

FIG. 15 shows a port information block;

FIG. 16 shows an example of protocol filtering;

FIG. 17 shows a look-up engine controller Instruction State Machine;

FIG. 18 shows a typical fast timing diagram; and

FIG. 19 shows a typical SIB RAM access instruction timing diagram.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

A typical look-up engine (LUE) in accordance with the invention isdesigned to be used in a twelve-port wire speed Ethernet to ATMbridge-router capable of switching about 178,000 packets per secondusing 64 byte minimum Ethernet packets. This packet rate corresponds toa look-up request occurring every 5.6 μsecs. The LUE is used each time apacket is received off the Ethernet or the ATM network. The type ofinformation that the engine provides depends on the direction of packetflow and the type of packet.

The look-up engine provides all the information needed to find the pathto each known destination, as well as default information in the case ofunknown destinations.

FIG. 1 shows a typical MAC layer header format for a packet that can beparsed with the aid of the look-up engine in accordance with theinvention. The header comprises destination and source address fields100, 101, a network layer protocol type field 102, and network layerdestination and source address fields 103, 104. FIG. 1 also illustrateshow the header is parsed in accordance with the invention. All fieldsexcept 102 are parsed using a tree search. The Net Layer Protocol Typefield 102 is parsed by using microcode comparisons in the microcodeengine to be described.

On a bridge-router, each port is represented by a corresponding bit in aPortSet (Ports 0-11), which is a 16 bit value that has localsignificance only. The Control Processor and ATM are each assigned aport.

The following definitions are special cases of a PortSet:

    ______________________________________    SinglePortSet    a PortSet with a single bit set.    HostPortSet    a SinglePortSet corresponding to the Control Processor    MyPortSet    a SinglePortSet corresponding to the source port of this packet.    NullPortSet    a PortSet of no parts.    ______________________________________

A Connection Identifier (CI), which is a 16 bit value with localsignificance only, is used to map connections into VPI/VCI values.

The following definitions are special cases of CI:

    ______________________________________    Mesh.sub.-- CI    a CI corresponding to a path towards the destination endstation's    Bridge-router.    Null.sub.-- CI    a CI connected to nothing. It is returned when the destination is    attached to the local Bridge-router or if the connection is not    allowed.    RS.sub.-- CI    a CI corresponding to a path to the Route Server.    ABS.sub.-- CI    a CI corresponding to a path to the Address/Broadcast Server.    ______________________________________

MAC layer addresses are globally unique 48 bit values, except in someprotocols such as DECNet, where they may not be globally unique.

    ______________________________________    Unicast.sub.-- DA    a MAC layer destination address of an end-station.    Router.sub.-- DA    a MAC layer destination address of the Route Server. An end-    station sends packets to the Route Server when it cannot send to    the destination directly at the MAC layer.    Broadcast.sub.-- DA    the broadcast MAC layer address (all ones) which is received by    all end-stations. It cannot be a source address.    Multicast.sub.-- DA    a multicast MAC layer address (group bit set) which is received by    end-stations that recognize that multicast address.    ______________________________________

Network layer (NL) addresses are network protocol dependent. They aregenerally divided into Network, Subnet, and Node portions, although notall protocols have all three present. The Network Layer Address FieldSizes (in bits) are summarized in the table below.

    ______________________________________    Protocol            Total Size                      Network   Subnet  Node    ______________________________________    IP      32        8/16/24   variable                                        variable    IPX     80        n/a       32      48                                        (MAC address)    AppleTalk            24        n/a       16      8    DECNet  64        16        38      10                      (reserved)                                (32 =                                'HIORD')                                (6 = subnet)    ______________________________________

The look-up engine handles unicast network layer addresses.

When the look-up engine is used in a bridge-router providing aninterface between an Ethernet and ATM network, packets coming from theEthernet side are fed into the Look-up Engine. The result of the look-uphas the form:

    ______________________________________    Input    ->  Command, CI, PortSet    ______________________________________

where Input is derived from the first few bytes of the packet andCommand is an opcode to the AXE (Transfer engine).

The Quad MAC status word distinguishes between router MAC, broadcast andmulticast MACs.

Bridging occurs when the destination address is a unicast address otherthan the Route Server address. Bridging is allowed between twoendstations in the same area for a given protocol.

Both source and destination MAC addresses must be known before automaticbridging/filtering is performed; otherwise, the packet is sent to theRoute Server for:

SA (Source Address) validation if the SA has never been seen speaking agiven protocol

DA (Destination Address) resolution if the DA was not found in the localMAC cache.

The Bridge command instructs the AXE (Transfer Engine) to use RFC-1483bridge encapsulation. BridgeProp command instructs the AXE to usebridge-router encapsulation (include source PortSet in encapsulation)

    ______________________________________    Unknown.sub.-- SA  -> BridgeProp, Null.sub.-- CI, HostPortSet, MyPortSet    * Unknown SA - send to HP for Spanning Tree processing    * HP will decide whether to forward it to ABS for learning,    depending on Spanning Tree state    Unicast.sub.-- DA  -> Bridge, Mesh.sub.-- CI, NullPortSet    * DA in the same area on a different Bridge-router    Unicast.sub.-- DA  -> Bridge, Null.sub.-- CI, NullPortSet    * DA not in the same area (reject)    * Protocol not allowed to bridge-router    * DA on the same port    Unicast.sub.-- DA  -> Bridge, Null.sub.-- CI, SinglePortSet    * DA in the same area on the same Bridge-router but on a different    port    Unknown.sub.-- DA  -> BridgeProp, ABS.sub.-- CI, NullPortSet, MyPortSet    * DA not found in the table - send to ABS for flood processing    Broadcast.sub.-- DA  -> BridgeProp, ABS.sub.-- CI, NullPortSet,    MyPortSet    * Broadcast DA - Send to Control Processor for broadcast    processing    Multicast.sub.-- DA  -> BridgeProp, ABS.sub.-- CI, NullPortSet,    MyPortSet    * Multicast DA - Send to ABS for multicast processing    Multicast.sub.-- DA  -> Bridgeprop, Null.sub.-- CI, HostPortSet,    MyPortSet    * Multicast DA is of interest to HP (eg Spanning Tree)    * HP will decide whether to forward it to ABS for multicast    processing    ______________________________________

Routing occurs when the destination address is the unicast Route Serveraddress. Filtering rules between areas are explicitly defined perprotocol The per protocol source area is an attribute of the source MACaddress and the per protocol destination area is an attribute of thedestination NL address.

Both source MAC and destination NL addresses must be known beforenetwork layer forwarding can occur.

The packet will be bridged to the Route Server if any of the followingare true:

IP options are present

Protocol is unknown

The packet will be dropped if any of the following are true:

Source area is not allowed to send to Destination area for this protocol

Source NL address is invalid (e.g. any IP broadcast address)

Checksum is invalid

Time-To-Live field expires

    ______________________________________    Unicast.sub.-- NLDA  -> Route, Mesh.sub.-- CI, NullPortSet    * NL node on a different bridge-router    Unicast.sub.-- NLDA  -> Route, Null.sub.-- CI, SinglePortSet    * NL node on the same bridge-router (could be same port)    Unknown.sub.-- NLDA  -> Bridge, RS.sub.-- CI, NullPortSet    * unknown NL node - send to Route Server    Unknown.sub.-- Protocol  -> Bridge, RS.sub.-- CI, NullPortSet    * protocol unknown, or packet with options    ______________________________________

FIG. 2 shows the data paths in a typical bridge-router. Controlprocessor 16 has control over the formatting of packets it sends andreceives. If the control processor 16 wants look-up engine 17 to performa look-up, it formats the packet in the same way as Quad Mac 15;otherwise it sends it as a raw packet, which does not require a lengthylook-up. The control processor predetermines the destination byproviding a CI (Connection Identifier) and an output Portset as part ofthe data stream. A bit in the Quad MAC status word indicates a rawpacket and the look-up engine simply retrieves the CI and Portset aspart of the data stream. A bit in the Quad MAC status word indicates araw packet and the look-up engine simply retrieves the CI and Portsetfrom the data stream and feeds it to the AXE (Transfer Engine) throughthe result FIFO. The Control processor is responsible for correctlyformatting the required encapsulation.

As shown in FIG. 2, packets coming from the ATM side are fed into thelook-up engine. The look-up engine accepts an RFC-1483 encapsulatedpacket and determines whether to look at a MAC or NL address. The resultof the look-up will have the form:

    ______________________________________    Input   ->  PortSet    ______________________________________

Filtering is not performed in this direction. It is assumed that the allfiltering is done at the ingress side. It is also assumed that thedestination endstation is known to be attached to the receivingBridge-router, so unicast packets with unknown destination addresses aredropped.

Flood and broadcast packets are encapsulated in a special format whichincludes an explicit output PortSet.

    ______________________________________    Unicast.sub.-- DA  -> SinglePortSet    * DA on this Bridge-router    Unknown.sub.-- DA  -> NullPortSet    * DA not in the table (drop) - this situation should not occur.    Unicast.sub.-- NLDA  -> SinglePortSet    * NLDA on this Bridge-router    Unknown.sub.-- NLDA  -> NullPortSet    * NLDA not in the table (drop) - this situation should not occur.    Broadcast.sub.-- DA,PortSet  -> PortSet    * Proprietary Broadcast request received from RS    Multicast.sub.-- DA,PortSet  -> PortSet    * Proprietary Multicast request received from RS    Unknown.sub.-- DA,PortSet  -> PortSet    * Proprietary Flood request received from RS    ______________________________________

Turning now to FIG. 3, the look-up engine consists of three functionalblocks, namely a destination address look-up engine (DALE) 1, a sourceaddress look-up engine (SALE) 2, and a look-up engine controller (LEC)3, which includes a microcode ram 4. DALE 1 includes a destinationaddress look-up controller 5 and DALE RAM 6. SALE 2 includes a sourceaddress look-up controller 7 and SALE RAM 8. The input to the look-upengine is through a fast 16-bit wide I/F RAM 9 receiving input from theAXE (Transfer Engine) and reassembler. The output from the look-upengine is through word-wide FIFOs 11, 12.

One embodiment of look-up engine controller (LEC) 3 is shown in moredetail in FIG. 4. This comprises (Station Information Block) SIB ram 20,interface ram 21, and microcode ram 22. The SIB ram 20 is connected tolook-up pointers 23. Interface ram 21 is connected to data register 25and index pointers 26 connected to ALU (Arithmetic Logic Unit) 27.Microcode ram 22 is connected to instruction register 28.

The look-up Engine controller 3 is a microcoded engine tailored forefficient bit pattern comparisons through a packet. It communicates withthe Source Address Look-up Engine 2 and the Destination Address Look-upEngine 1, which both act as co-processors to the LEC 3.

The look-up engine snoops on the receive and transmit data buses anddeposits the header portion of the packet into the I/F RAM 9. Thelook-up response is sent to the appropriate FIFO 11, 12.

FIGS. 5 show an alternative embodiment of the loop-up engine andcontroller. In FIG. 5, the LEC 3 includes a 64×16 I/F (Interface) ram 41connected to FIFO's 42, 43 (First-in, First-out memories) respectivelyconnected to latches 44, 45 receiving AXE (Transfer Engine) andreassembler input.

Referring now to FIG. 6, the LEC 3 also contains several registers,which will now be described. Register select instructions are providedfor the register banks (XP0-7, LP0-7).

Index Pointer register (IP) 50 is a byte index into the I/F RAM 21.Under normal operation, the index pointer register 50 points to thecurrent packet field being examined in the I/F RAM 21 but it can be usedwhenever random access to the I/F RAM 21 is required.

The IP 50 can be modified in one of the following ways:

1) loaded by the LOADIP instruction (e.g. to point to the beginning ofthe packet)

2) incremented by 1 (byte compare) or 2 (word compare) if a branchcondition is not met.

3) incremented by 2 by a MOVE (IP)+ type instruction.

Data Register 51 contains the 16 bit value read from I/F RAM 21 usingthe current IP. The DR 51 acts like a one word cache; the LEC keeps itscontents valid at all times.

Program Counter 52 points to the current microcode instruction. It isincremented by one if a branch condition is true, otherwise thedisplacement field is added to it.

The Lookup Pointers (LP0-7) 23 are 16 bit registers which containpointers to the SIB RAM 20. The LPs are used to store pointers whenevermilestones are reached in a search. One LP will typically point to asource SIB and another will point to a destination SIB. The LP providesthe upper 16 bits of the pointer; the lower 4 bits are provided by themicrocode word for indexing into a given SIB.

The LPs are also used to prime the SALE and DALE with their respectiveroot pointers.

X,Y Registers 53, 54 are general purpose registers where logicmanipulations can be made (AND, OR, XOR). They are used for setting andclearing bits in certain words in the SIB RAM (e.g. Age bit) and to testfor certain bits (e.g. status bits). The X Register 53 can be selectedas Operand A to the Logic Unit while the Y Register can be selected asOperand B.

The BYZ and BYNZ instructions conditionally branch on Y=0 and Y<>0respectively.

The Y Register 54 is the only register source for moves to the resultFIFOs.

The X Register 53 can be saved to or restored from X' Registers(X'0-X'7) 55. The mnemonic symbol for the currently selected X' registeris XP.

The S Register 56 is a pipelining stage between SIB RAM 20 and the LogicUnit. It simplifies read access from SIB RAM 20 by relaxing propagationdelay requirements from SIB RAM 20 valid to register setup. It providesthe added advantage of essentially caching the most recent SIB RAMaccess for repeated use. It is loaded by the GET Index(LP) instruction.

As in FIG. 3, the LEC 3 controls the operation of the look-up engine.All look-up requests pass through the LEC 3, which in turn activates theSALE 2 and the DALE 5 as required. The LEC 3 is microcode based, runningfrom a 32-bit wide microcode RAM. The instruction set consists mainly ofcompare-and-branch instructions, which can be used to find specific bitpatterns or to check for valid ranges in packet fields. Special I/Oinstructions give the LEC random read access to the interface RAM.

The LEC has access to 3 memory systems: the interface RAM 9, the SIB RAM20 and the Microcode RAM 22.

The interface RAM 9 is used to feed packet data into the LEC 3. Thelook-up engine hosts dump packet headers into this RAM through snoopFIFOs 42, 43. This RAM is only accessible through the snooped buses.

The SIB RAM 20 is used to hold information for each known end-station.The LEC 3 can arbitrarily retrieve data from this RAM and transfer it toone of the response FIFOs 11, 12 or to internal registers formanipulation and checking. High speed RAM is also used to minimize thedata retrieval time. The size of the SIB RAM 20 is dependent on themaximum number of reachable end-stations. For a limit of 8,000end-stations, the SIB RAM size is 256K bytes. This RAM is accessibledirectly to the Control Processor for updates.

The Microcode RAM 22 is dedicated to the LEC 3. It contains the 32 bitmicrocode instructions. The LEC 3 has read-only access to this highspeed RAM normally, but it is mapped directly to the Control Processor'smemory space at startup for microcode downloading.

Variable fields of a packet, such as addresses, are searched in one ofmany search trees in the ALEs 1, 2, (FIG. 5), which are nibble indexmachines. Each ALE 1, 2 has its own search tree RAM 6, 8 (FIG. 7), whichis typically high density but low speed. This RAM is divided into 32byte blocks which can either be Index Arrays or Information Blocks.

The searches in the ALEs 1, 2 are based strictly on the root pointer,the search key and search key length it is given. A look at the look-upengine memory map (FIG. 7) as viewed from the ALEs shows how themechanism works.

All search trees in a given ALE 6, 8 reside in the upper half of itsmemory. The 16-bit root pointer given to the ALE will have the mostsignificant bit set. The search key (e.g. MAC address) is divided intonibbles. The first nibble is concatenated with the root pointer to getan index into the root pointer array. The word at this location isretrieved. If the MSB (Most Significant Bit) (P Bit) is set, the nextnibble is concatenated with the retrieved word to form the next pointer.If the P Bit is clear, the search is finished. The final result is givento the LEC, which uses it either as a pointer into the SIB RAM, or asdata, depending on the context of the search. A zero value is reservedas a null pointer value. FIG. 8 illustrates search tree operation.

The search key length limits the number of iterations to a knownmaximum. The control processor manipulating the search tree structuremay choose to shorten the search by putting data with a zero P bit atany point in the tree.

"Don't Care" fields are also achievable by duplicating appropriatepointers within the same pointer array. Search trees are maintained bythe Control Processor, which has direct access to the SALE and DALE RAMs6, 8.

FIG. 9 is a diagram illustrating a MAC search tree example. The mainpurpose of the ALE RAMs 6, 8 is to hold MAC layer addresses. The size ofthe RAM required for a MAC address tree depends on the statisticaldistribution of the addresses. The absolute worst case is given by thefollowing formula: ##EQU1##

where

X is the number of addresses

L is the number of nibbles in the address

N is the number of pointer arrays

The amount of memory required, given 32-byte pointer arrays, is 32N. Thenumber obtained from this formula can be quite huge, especially for MACaddresses, but some rationalizations can be made.

In the case of MAC addresses, the first 6 nibbles of the address is theOrganizationally Unique Identifier (OUI), which is common to Ethernetcards from the same manufacturer. It can be assumed that a particularsystem will only have a small number of different OUIs.

The formula for MACs then becomes: ##EQU2##

where

M is the number of different OUIs

X_(j) is the number of stations in OUI_(j)

Assuming that the addresses are distributed evenly over all OUIs,##EQU3##

The effect of OUI on Search Tree Size is shown in FIG. 10.

Similar rationalizations can be made with IP and other network layerprotocol addresses. An IP network will not have very many subnets andeven fewer network numbers.

Although the SALE 2 typically holds locally attached source MACaddresses and the DALE 1 typically holds destination MAC addresses,either ALE 1, 2 is capable of holding any arbitrary search tree. Networklayer addresses, intra-area filters, and user-defined MAC protocol typescan all be stored in search trees. The decision to put a search tree ineither SALE or DALE is implementation dependent; it relies on whatsearches can be done in parallel for maximum speed.

The principal function of the SALE 2 is to keep track of the MACaddresses of all stations that are locally attached to thebridge-router. Typically one station will be attached to a bridge-routerport, but connections to traditional hubs, repeaters and bridge-routersare allowed, so more source addresses will be encountered.

Using the formula for RAM size above, typical RAM calculations for thesource address trees are as follows:

    ______________________________________                    Number of    Number of OUIs  Stations Total Bytes    ______________________________________    20              400      65,440    2               500      65,184    20              500      77,984    20              800      116,284    5               1,000    131,552    ______________________________________

The number of source stations is limited to some fraction of the totalallowable stations. The limit is imposed here because the SALE will mostlikely hold many of the other search trees (e.g. per protocol NL addresssearch trees, intra-area filters).

Whenever a new source address is encountered, the SALE 1 will not findit in the MAC source address search tree. The LEC 3 realizes the factand sends it to the Control Processor. The new source address isinserted into the search tree once validation is received from the RouteServer.

Whenever a previously learned address is re-encountered, the Age entryin the SIB 20 is refreshed by the LEC 3. The control processor clearsthe Age entry of all source addresses every aging period. The entry isremoved when the age limit is exceeded.

The source address look-up engine table is shown in FIG. 11.

The DALE 1 keeps track of all stations that are directly reachable fromthe bridge-router, including those that are locally attached. The DALEsearch trees are considerably larger because they contain MAC addressesof up to 8,000 stations.

Typical memory sizes for MAC destination address search trees would be:

    ______________________________________    Number of      Number of    OUIs           Stations Total Bytes    ______________________________________    10             8,000    856,992    20             8,000    945,824    30             8,000    1,034,464    ______________________________________

A station's MAC address will appear in the MAC search tree if thestation is reachable through MAC bridging. A station's network layeraddress will appear in the corresponding network layer search tree if itis reachable through routing.

The destination address look-up engine MAC table is shown in FIG. 12.

IP masking may be required if a particular port is known to have arouter attached to it. Masking is achieved by configuring the IP networklayer search tree in such a way that the node portion of the address istreated as Don't Care bits and the corresponding pointers point to thesame Next Index Array.

The SALE and DALE RAMs 8, 6 are divided up into 16 word blocks. TheseRAMs are accessible only to the corresponding ALE and the ControlProcessor. These RAMs contain mostly pointer arrays organized in severalsearch trees.

The SIB RAM 20 is divided into 16 word blocks which can be treated asrecords with 16 fields. Each block typically contains information aboutan endstation. This RAM is accessible only to the LEC and the CP.

The LEC 3 uses the lookup pointer (LP) as a base pointer into a SIB 20.The contents of the LP is obtained either from the result of a SALE 2 orDALE 1 search to access end-station information, or from a constantloaded in by the microcode to access miscellaneous information (e.g.port information). The LP provides the upper sixteen bits and themicrocode word provides the lowest four bits of the SIB RAM address.

The lookup Engine addressing scheme is shown in FIG. 13.

The SIB RAM 20 (FIG. 14) generally contains information about thelocation of an endstation and how to reach it. For example, the PortSetfield may keep track of the port that the endstation is attached to (ifit is locally attached) and the connection index refers to a VPI/VCIpipe to the endstation (if it is remotely attached). Other fields arefreely definable for other things such as protocol filters, source anddestination encapsulation types and quality-of-service parameters, asthe need arises.

A variant of the SIB is the Port Information Block (PIB) (FIG. 15). PIBscontain information about a particular port. Certain protocols haveattributes attached to the port itself, rather than the endstations. Anendstation inherits the characteristics assigned to the port to which itis attached.

The definition of the SIB is flexible; the only requirement is that thedata be easily digestible by the LUE instruction set. The field type canbe a single bit, a nibble, a byte, or a whole word.

In FIG. 14, the CI (Connection Identifier) field is a reference to anATM connection to the endstation if it is remotely attached. This fieldis zero for a locally attached endstation.

The PortSet field is used both for determining the destination port of alocally attached endstation, and for determining whether a sourceendstation has moved. In one Newbridge-router Networks system, a movedendstation must go through a readmission procedure to preserve theintegrity of the network. This field is zero for a remotely attachedendstation.

The MAC Index is a reference to the 6-byte MAC layer address of theendstation. This field is used for network layer forwarded packets,which have the MAC layer encapsulation removed. The MAC layer address isre-attached when a packet is re-encapsulated before retransmission outan Ethernet port. The encapsulation flags determine the MACre-encapsulation format.

The Proto Area and Proto Dest Area fields are used for filteringoperations. Because the Newbridge-router system essentially removes thetraditional physical constraints on a network topology, the area conceptlogically re-imposes the constraints to allow existing protocols tofunction properly. Filtering rules defined between areas determinewhether two endstations are logically allowed to communicate with eachother using a specific protocol.

The Proto Area field is a pointer to a filtering rule tree, which issimilar in structure to the address trees. The Dest Area field is asearch key into the tree. The result of the search is a bitfield inwhich each protocol is assigned one bit. Communications is allowed ifthe corresponding bit is set.

FIG. 16 shows a filtering rule tree.

The microcode for the LEC 3 will now be described. The LEC microcode isdivided into four main fields as shown in the table below. The usage ofeach field is dependent on the instruction group.

    ______________________________________    31-29     28-24      23-16        15-0    ______________________________________    Inst      Instruction                         Displacement Parameter    Group    ______________________________________

The instruction group field consists of instructions grouped accordingto similarity of function. A maximum of eight instruction groups can bedefined.

The Instruction field definition is dependent on Instruction Group.

In branch instructions, the Displacement field is added to the PC if thebranch condition is true. This field is used by non-branch instructionsfor other purposes.

The Parameter field is a 16 bit value used for comparison, as anoperand, or as an index, dependent on the instruction.=

The functions of the groups are set out in the following table.

    ______________________________________    Group 0       Index Pointer/Bank Select                  Instructions                  These instructions manipulate the                  IP and the register bank select                  register.    Group 1       Fast Move Instructions                  These instructions move data                  between I/F RAM and internal                  registers.    Group 2       Conditional Branch Instructions                  These instructions branch when a                  given condition is met. They can                  optionally increment the IP.    Group 3       X Register Branch Instructions                  These instructions branch on an X                  Register logic comparison.    Group 4       Not Used    Group 5       Slow Move Instructions                  These instructions generally                  involve the SIB RAM bus. The                  access time to the SIB RAM is                  longer because of address setup                  time considerations and because                  the CP may be accessing it at the                  same time. Access to the Result                  FIFOs are included here.    Group 6       Not Used    Group 7       Misc Instructions                  These instructions invoke special                  functions.    ______________________________________

The following table describes the use of each of the fields.

    __________________________________________________________________________                           17-16    Grp       31-29           28-26               25-24                   23-21                       20-18                           18-16*                               15-0    __________________________________________________________________________    0  0 0 0           0 0 0 Oper. 1 1 1 1 1 0 BSel                               Immediate Value (15-0)                               or                               Register Select (15-4)    1  0 0 1           Dest.               Size                   LSel                       ASel                           BSel                               Immediate Value (15-0)                               Register Select (15-4)                               or Index (3--0)    2  0 1 0           Cond.               Size                   Disp. (8)   Comparand    3  0 1 1           Cond.               0 0 LSel                       Disp. (5)                               Comparand    4  1 0 0    5  1 0 1           Dest.               Size                   LSel                       ASel                           BSel                               Immediate Value (15-0)                               Register Select (15-4)                               or Index (3--0)    6  1 1 0    7  1 1 1           0 0 0               Size                   0 0 0                       0 0 0                           0 0 codes    __________________________________________________________________________     *when LSel = 110

    ______________________________________    Condition    ______________________________________    000 - (IP) = Comparand    001 - (IP) < Comparand    010 - (IP) > Comparand    011 - True    100 - Extended Condition = True    101 - Extended Condition = False    110 - Y = 0    111 - Y <> 0    Dest - Destination    000 - currently active FIFO    001 - X Register    010 - Lookup Engine Address RAM    011 - Group 5: S Register      otherwise: None    100 - Y Register    101 - Index (LP) (SIB RAM)    110 - XP Register    111 - Lookup Pointer    Operation - IP/Register Select operation    00 - Register Select    10 - Load    Size - IP increment size    00 - no increment    01 - byte (+1)    10 - word (+2)    Displacement (8 bits)    00000001 - next instruction    00000000 - same instruction    Displacement (5 bits)    00001 - next instruction    00000 - same ihstruction    LSel - Logic Unit Select    000 - A AND B    001 - A OR B    010 - A AND NOT B    011 - A OR NOT B    100 - A XOR B    101 - Reserved    010 - B    111 - A    ASel - Operand A Select    000 - (IP), (IP)+               Indirect I/F Data    001 - X    X Register    010 - S    S Register    011 - XP   X' Register    100 - XP   X' Register    101 -    110 -    111 -    BSel - Operand B Select    00 - Y     Y Register    01 - #Value               Immediate Value    11 -       Special Function    When LSel = 110:    010 - DALE Lookup Result    110 - SALE Lookup Result    Immediate Value    Word values fill the whole field    Byte values must be repeated twice to fill the field    When BSel = 11 (Special Functions):    Value    Function      Mnemonic    $0000    X rotate left 4                           L4(X),R12(X)    $1000    X rotate 8 (byte swap)                           SWAP(X),L8(X),R8(X)    $2000    X rotate right 4                           R4(X),L12(X)    $3000    portset(X)    PSET(X)    $4000    X rotate left 1                           L1(X)    $5000    X rotate right,1                           R1(X)    $6000    flip X        FLIP(X)    $7000    LUE Version number                           VER    When Value = $3000 (Portset Function):    X(11:8)  f(15:0)    0        0000000000000001    1        0000000000000010    2        0000000000000100    3        0000000000001000    4        0000000000010000    5        0000000000100000    6        0000000001000000    7        0000000010000000    8        0000000100000000    9        0000001000000000    10       0000010000000000    11       0000100000000000    12       0001000000000000    13       0010000000000000    14       0100000000000000    15       1000000000000000    ______________________________________

FIFO Write Instructions

    ______________________________________    31-29  28-26   25-24   23-21 20-18 17-16 15-0    ______________________________________    1 0 1  0 0 0   0 0     1 1 0 Extra BSel  Immediate                                             Value (15-0)    ______________________________________

    __________________________________________________________________________    0ee 01 MOVEF #Value,Extra                Move Immediate Value to FIFO with Extra bits    0ee 00 MOVEF Y,Extra                Move Y Register to FIFO with Extra bits    1ee 00 MOVEF Index(LP),Extra                Move Indexed Lookup Data to FIFO with Extra    __________________________________________________________________________                bits

The FIFO write instructions are used to write data into the currentlyactive result FIFO. The Extra field control bits 16 and 17 in the FIFOdata bus.

The third instruction in the list is a direct memory access from SIB RAMto the active FIFO. SIB RAM is enabled while the active FIFO is sent awrite pulse. Doing so avoids having SIB data propagate through the LUE.Bit 20 differentiates between a DMA and a non-DMA instruction.

The X register cannot be used as a MOVEF source because what wouldnormally be the ASel field conflicts with the Extra field.

Usage:

    ______________________________________    MOVEF  #IPSnap,0  ; Packet is IP over SNAP    Interface RAM Data Read Instructions    ______________________________________

    ______________________________________    31-29  28-26   25-24   23-21 20-18 17-16 15-0    ______________________________________    0 0 1  Dest    Size    1 1 1 0 0 0 0 0   Unused    ______________________________________

    ______________________________________    Dest/Size    ______________________________________    001 00   MOVE  (IP),X             Move IP indirect to X Register    001 10   MOVE  (IP)+,X             Move Ip indirect autoinc to X Register    100 00   MOVE  (IP),Y             Move IP indirect to Y Register    100 10   MOVE  (IP)+,Y             Move IP indirect autoinc to Y Register    111 00   MOVE  (IP),LP             Move IP indirect to LP Register    111 10   MOVE  (IP)+,LP             Move IP indirect autoinc to LP Register    ______________________________________

Interface RAM Data Read instructions are used to read data from theInterface RAM 41 into the X, Y or LP Register. The LP used ispreselected using the RSEL instruction.

Lookup Pointer Instructions

    ______________________________________    31-29  28-26   25-24   23-21 20-18 17-16 15-0    ______________________________________    Group  Dest    0 0     LSel  ASel  BSel  Immediate                                 or          Value (15-0)                                 Extra       Reg Sel                                             (15-4)                                             or Index                                             (3-0)    ______________________________________

    ______________________________________    Group/Dest/LSel/ASel/BSel - Instruction Type    ______________________________________    101 101 111 001 00                  MOVE X,Index(LP)                  Move X Register to Indexed Lookup Data    101 101 110 000 00                  MOVE Y,Index(LP)                  Move X Register to Indexed Lookup Data    101 011 000 000 00                  GET Index(LP)                  Load S Register with Indexed Lookup Data    001 111 110 000 00                  MOVE Y,LP                  Move X Register to Lookup Pointer    001 111 110 000 01                  MOVE #Value,LP                  Move Immediate Value to Lookup Pointer    001 111 111 001 00                  MOVE X,LP                  Move X Register to Lookup Pointer    ______________________________________

Lookup Pointer instructions are used to load the Lookup Pointers or tostore and retrieve values in Lookup RAM.

Usage:

    ______________________________________    MOVE         Age(LP),X    ; Get Age field    . . .                     ; check age    . . .                     ; reset age    MOVE         X,Age(LP)    ; put it back in    ______________________________________

Logic Instructions

    ______________________________________    31-29  28-26   25-24   23-21 20-18 17-16 15-0    ______________________________________    0 0 1  Dest    0 0     LSel  ASel  BSel  Immediate                                             Value (15-0)                                             or Index                                             (3-0)    ______________________________________

Logic instructions are used to perform logic manipulations on the X andY Registers. Combinations of the selections above yield the following(useful) instructions:

    ______________________________________    Dest/LSel/ASel/BSel    ______________________________________    001 110 000 00     MOVE Y,X                       Y -> X    100 111 001 00     MOVE X,Y                       X -> Y    001 111 010 00     MOVE S,X                       S -> X    100 111 010 00     MOVE S,Y                       S -> Y    001 110 000 01     MOVE #Value,X                       Immediate Value -> X    100 110 000 01     MOVE #Value,Y                       Immediate Value -> Y    001 000 001 00     AND X,Y,X                       X AND Y -> X    001 000 010 00     AND S,Y,X                       S AND Y -> X    001 000 001 01     AND X,#Value,X                       X AND Value -> X    001 000 010 01     AND S,#Value,X                       S AND Value -> X    100 000 001 00     AND X,Y,Y                       X AND Y -> Y    100 000 010 00     AND S,Y,Y                       S AND Y -> Y    100 000 001 01     AND X,#Value,Y                       X AND Value -> Y    100 000 010 01     AND S,#Value,Y                       S AND Value -> Y    OR, ANDN, ORN and XOR are similar to AND:    dst 001 aaa bb     OR aaa,bb,dst                       aaa OR bb -> dst    dst 010 aaa bb     ANDN aaa,bb,dst                       aaa OR bb -> dst    dst 011 aaa bb     ORN aaa,bb,dst                       aaa OR bb -> dst    dst 100 aaa bb     XOR aaa,bb,dst                       aaa OR bb-> dst    ______________________________________

Conditional Branch Instructions

    ______________________________________    31-29    28-26    25-24    23-16     15-0    ______________________________________    0 1 0    Cond.    Size     Displacement                                         Comparand    ______________________________________

    ______________________________________    Cond/Size    ______________________________________    000 01        ESCNE.b  #Comparand,Label                  Escape if Byte Not Equal    000 10        ESCNE.w  #Comparand,Label                  Escape if Word Not Equal    001 01        ESCGE.b  #Comparand,Label                  Escape if Byte Greater or Equal    001 10        ESCGE.w  #Comparand,Label                  Escape if Word Greater or Equal    010 01        ESCLE.b  #Comparand,Label                  Escape if Byte Less or Equal    010 10        ESCLE.w #Comparand,Label                  Escape if Word Less or Equal    110 00        BYZ Label                  Branch if Y Register is zero    111 00        BYNZ Label                  Branch if Y Register is not zero    ______________________________________

Increment Branch instructions are used to compare the current packetfield with an immediate value. If the condition is met, the branch istaken; otherwise IP is incremented by the Increment Size.

Usage:

    ______________________________________    Labell:              ; check if SNAP header    ESCNE. w   #$AAAA,Labe12 ; compare to SNAP value    ESCNE.w    #$0003,OtherLabel    . . .    Labe12:    ______________________________________

X Register Branch Instructions

    ______________________________________    31-29    28-26    25-24    23-21  20-16  15-0    ______________________________________    0 1 1    Cond     0 0      LSel   Disp   Value    ______________________________________

    ______________________________________    Cond/LSel    ______________________________________    110 100   BXEQ  #Value,Label              Branch if X is equal to value    111 100   BXNE  #Value,Label              Branch if X is not equal to value    110 000   ANDBZ  #Value,Label              Branch if X AND Value is equal to zero    111 000   ANDBNZ #Value,Label              Branch if X AND Value is not equal to zero    110 010   ANDNBZ #Value,Label              Branch if X AND NOT Value is equal to zero    111 010   ANDNBNZ #Value,Label              Branch if X AND NOT Value is not equal to zero    ______________________________________

X Register Branch instructions are derived from the X Register Logicinstructions with Operand A always set to the X Register and Operand Balways set to the Immediate value. The X Register is not affected by anyof these instructions. The displacement field is reduced to 5 bits(+/-32 instructions)

Usage:

    ______________________________________    See Destination Lookup Instruction example    SKIP.w  ; ignore the next word field    ______________________________________

Other Branch Instructions

    ______________________________________    31-29  28-26    25-24    23-16  15-4    3-0    ______________________________________    0 1 0  Cond     Size     Disp   ExtCond ExtDisp    ______________________________________

    ______________________________________    Cond/Size/Disp/ExtCond/ExtDisp.    ______________________________________    100 00 $00 $000 0 DWAIT                Wait for DALE    100 00 $00 $800 0 SWAIT                Wait for SALE    101 00 $00 $C00 0 FWAIT                Wait for Snoop FIFO done    101 00 ddd $400 0 BCSERR ddd                Branch on checksum error    011 01 $01 $000 0 SKIP.b                Skip Byte (same as IBRA.b +1)    011 10 $01 $000 0 SKIP.w                Skip Word (same as IBRA.w +1)    011 01 ddd $000 0 IBRA.b    Label                Increment Byte and Branch Always    011 10 ddd $000 d IBRA.w    Label                Increment Word and Branch Always    011 00 000 $800 0 SWITCH                Switch on X (add X to PC)    011 00 ddd $000 d BRA.u Label                Branch Always    ______________________________________

These instructions are derived from the conditional branch instructions.Wait instructions loop until the extended condition is false. Skipinstructions move to the next instruction and increment the IPappropriately.

More branch instructions can be defined easily by using Cond=100 or 101and picking an unused ExtCond pattern.

When Cond=011 (True), the displacement field is extended to 12 bits.

The SWITCH instruction adds the least significant nibble of X to the PC.If X(3:0)=0, 16 is added to the PC.

Usage:

    ______________________________________    SKIP.w  ; ignore the next word field    Index Pointer/Register Select Instructions    ______________________________________

Index Pointer/Register Select Instructions

    ______________________________________    31-29 28-26   25-24   23-21 20-18 17-16 15-0    ______________________________________    Group Dest    Oper    LSel  ASel  BSel  Immediate                                            Value (15-0)                                            or                                            Register Select                                            (15-4)    ______________________________________

    ______________________________________    Group/Dest./Oper/LSel/ASel/BSel    ______________________________________    001 110 00 111 000 00 ST                    X ,XPn,LPn!                    X -> XP, optionally switch to XPn,LPn    001 001 00 111 100 00 LD                    X{,XPn,LPn!                  XP -> X, optionally switch to XPn,LPn    001 011 00 111 000 00 RSEL                    XPn,LPn                    switch to XPn,LPn    000 011 10 111 000 01 LOADIP    # Value                  Load IP immediate    000 011 10 111 001 00 LOADIP    X                  Load IP with X    ______________________________________

Index Pointer instructions are used to perform manipulations on theindex pointer.

Transfers from the X registers are not normally used in a lookupfunction but may be useful for general purpose transfers from interfaceRAM.

The Register Select instruction selects a register from each of theregister banks. The format of the Bank Select Bits field is:

    ______________________________________    15-12     11      10-8    7     6-4    3-0    ______________________________________    X X X X   XEn     XSel    LPEn  LPSel  X X X X    ______________________________________

The En bits determine whether the corresponding select bits are valid.If En is zero, the corresponding register selection remains unchanged.If En is one, the corresponding select bits are used. This mechanismallows register selections to be made independent of each other.

Destination Lookup Instructions

    ______________________________________    31-29  28-26   25-24   23-21 20-18 17-16 15-0    ______________________________________    0 0 1  0 1 0   Size    1 1 1 ASel  0 0   Command/                                             Address    ______________________________________

    ______________________________________    Size/ASel    ______________________________________    00 001  DLOAD X,Address  ,Command!            Load X into DALE    00 000  DLOAD (IP),Address  ,Command!            Load IP indirect into DALE / load Command Reg    10 000  DLOAD (IP)+,Address  ,Command!            Load IP indirect autoinc into DALE / load Command    ______________________________________            Reg

    ______________________________________    31-29 28-26    25-24   23-21  20-18 17-16  15-0    ______________________________________    0 0 1 Dest     0 0     1 1 0  0 0 0 1 0    not used    ______________________________________

    ______________________________________    Dest    ______________________________________    111       DMOVE LP              Move DALE result pointer into Lookup Pointer    001       DMOVE X              Move DALE result pointer into X Register    100       DMOVE Y              Move DALE result pointer into Y Register    ______________________________________

The destination lookup instructions set up the DALE and read resultsfrom it. The currently selected lookup pointer is used as the rootpointer.

The DLOAD instruction loads words into the 16 by 16 bit DALE Nibble RAMand loads the Command Register. The DMOVE instruction returns the DALEresult.

Command Register

    ______________________________________    15      14      13-12     11-4       3-0    ______________________________________    Start   0       Nibble    0 0 0 0 0 0 0 0                                         Address                    Offset    ______________________________________

The Start bit signals the DALE to start the lookup.

The Nibble Offset field points to the first valid nibble in the firstword loaded into the Address RAM.

The Address field points to the word being written in Nibble RAM.

The DMOVE instruction gets the 16 bit DALE result pointer. DMOVE shouldbe preceded by DWAIT, otherwise the result may be invalid.

Usage:

    ______________________________________    LOADIP  #StartOfPacket                         ; point to start of packet    DLOAD   (IP)+, Word1 ; load DA word 1    DLOAD   (IP)+,Word2  ; load DA word 2    DLOAD   (IP)+,Word3,Start                         ; load DA word 3 and start lookup    . . .                : do other stuff    DMOVE   X            ; get result    BXNE    #Null,DAFound                         ; address found in table    ______________________________________

Source Lookup Instructions

    ______________________________________    31-29  28-26   25-24   23-21 20-18 17-16 15-0    ______________________________________    0 0 1  0 1 0   Size    1 1 1 ASel  0 1   Command/                                             Address    ______________________________________

    ______________________________________    Size/ASel    ______________________________________    00 001  SLOAD X,Address  ,Command!            Load X into SALE    00 000  SLOAD (IP),Address  ,Command!            Load IP indirect into SALE / load Command Word    10 000  SLOAD (IP)+,Address  ,Command!            Load IP indirect autoinc into SALE / load Command    ______________________________________            Word

    ______________________________________    31-29  28-26   25-24   23-21 20-18 17-16 15-0    ______________________________________    0 0 1  Dest    0 0     1 1 0 0 0 1 1 0   Immediate                                             Value (15-0)    ______________________________________

    ______________________________________    Dest    ______________________________________    111       SMOVE LP              Move SALE result pointer into Lookup Pointer    001       SMOVE X              Move SALE result pointer into X Register    100       SMOVE Y              Move SALE result pointer into Y Register    ______________________________________

The destination lookup instructions set up the SALE and read resultsfrom it. The currently selected lookup pointer is used as the rootpointer.

The SLOAD instruction loads words into the 16 by 16 bit SALE Nibble RAMand loads the Command Word. The SMOVE instruction returns the SALEresult.

Command Word

    ______________________________________    15       14      13-12     11-4       3-0    ______________________________________    Start    0       Nibble    0 0 0 0 0 0 0 0                                          Address                     Offset    ______________________________________

The Start bit signals the SALE to start the lookup.

The Nibble Offset field points to the first valid nibble in the firstword loaded into the Address RAM.

The Address field points to the word being written in Address RAM.

The SMOVE instruction gets the 16 bit SALE result pointer. The SMOVEinstruction should be preceded by SWAIT, otherwise the result may beinvalid.

Usage:

    ______________________________________    SLOAD    (IP)+,Word1  ; load DA word 1    SLOAD    (IP)+,Word2  ; load DA word 2    SLOAD    (IP)+,Word3,Start                          ; load DA word 3 and start lookup    . . .                 ; do other stuff    SWAIT                 ; wait for SALE to finish    SMOVE    X            ; get result    BXNE     #Null,SAFound                          ; address found in table    ______________________________________

Checksum Engine Instructions

    ______________________________________    31-29 28-26    25-24   23-21  20-18 17-16  15-0    ______________________________________    0 0 1 0 1 0    Size    1 1 1  ASel  1 0    $8000    ______________________________________

    ______________________________________    Size/ASel    ______________________________________    00 001  CLOAD X            Load X into Checksum Engine and start    00 000  CLOAD (IP)            Load IP indirect into Checksum Engine and start    10 000  CLOAD (IP)+            Load IP indirect autoinc into Checksum Engine and    ______________________________________            start

The CLOAD instruction loads a word count into the checksum engine,clears the checksum and starts the engine. The word currently indexed byIP is subsequently added to the checksum each time the IP crosses a wordboundary until the count is exhausted.

Miscellaneous Instructions

    ______________________________________    31-29        28-16         15-0    1 1 1        0 0 0 0 0 0 0 0                               Code (2-0)    ______________________________________

These instructions invoke special functions

    ______________________________________    Code    001         STOP                Stop execution until next lookup request    ______________________________________

The lookup engine operation will now be described in more detail. Theinstruction State Machine (ISM) is shown in FIG. 17.

A lookup engine microcode will typically take four clock cycles. At 50MHz, the instruction cycle takes 80 ns to execute. Instructions thatrequire access to SIB RAM, which require arbitration with the ControlProcessor, and any future extensions that require more time to executewill require one or more additional cycles to complete.

After reset, the 3 LEC is in the idle state. As soon as one of the snoopFIFOs 42, 43 is non-empty, the ISM enters the main instruction cycleloop.

A microcode instruction cycle is typically divided into four mainstates. State 3 and State 0 allow the microcode contents to propagatethrough the LEC. The instruction group is determined in State 1. If afast instruction is being executed (Groups 0-3), State 2 is enteredimmediately. Otherwise the appropriate next state is entered accordingto the Group field.

FIG. 18 shows a typical fast instruction.

By the time State 2 is reached, all signals will have settled. Newvalues for the PC and if necessary, the IP and/or the selecteddestination, are loaded at the end of this state.

State 42 is a dummy state for currently undefined groups.

State 52 is a wait state for external accesses to SIB RAM. The ISM exitsthis state when the SIB RAM has been granted to the LEC long enough foran access to complete.

FIG. 19 shows a typical SIB RAM access instruction.

States 72 and 73 are executed during the STOP instruction. State 73flushes the snoop FIFOs in case.

The LEC cycles through States 0 to 3 indefinitely until a STOPinstruction is encountered, which brings the LEC back to the idle state.

The lookup request mechanism for a MAC layer lookup is as follows:

The requester (e.g. the AXE) places information, generally a packetheader, into the snoop FIFO.

The empty flag of the FIFO kickstarts the LEC.

The LEC instructs the DALE to look up the destination address.

The LEC instructs the SALE to look up the source address.

The LEC looks into the packet to determine the network layer protocol incase it needs to be forwarded.

The LEC waits for the SALE and reads the Source Address SIB pointer.

The source port is compared against the previously stored portset to seeif the source endstation has moved.

The LEC waits for the DALE and reads the Destination Address SIBpointer.

The destination area is compared to the source area to see if theendstations are in the same area.

The source port is compared against the destination port to see if theendstations are on the same port.

Packets are discarded if they serve no other useful purpose (e.g. SA andDA on the same port or in different areas, errored packets). Otherwisethey are sent to the Control Processor for further processing.

Sample Program

    __________________________________________________________________________    ;-------------------------------    ; File: BDG.a    ; Unicast Bridging Case    ; Release 1.1 Functionaiity    ;-------------------------------    BDG.sub.-- Start:    ;XO = Packet Status Word    ;IP = Points to 2nd byte of PSW    ;DR = Contains Packet Status Word    ;XO, LPO are default XP, LP       MOVE           $8000,LP                  ;Look up Destination MAC      DLOAD           (IP)+,0                  ;Load Dst Addr bits 0-15      DLOAD           (IP)+,1                  ;Load Dst Addr bits 16-31              ;Load Dst Addr bits 32-47       DLOAD           (IP)+,2,$8000                  ;and start lookup       MOVE           $8000,LP                  ;Look up Source MAC      SLOAD           (IP)+,0                  ;Load Src Addr bits 0-15      SLOAD           (IP)+,1                  ;Load Src Addr bits 16-31              ;Load Src Addr bits 32-47       SLOAD           (IP)+,2,$8000                  ;and start lookup    ; determine protocol here       ESCGE.w              1500,CheckEnetType                     ;check if 802.3 format      ESCNE.w $AAAA,UnknownType                     ;check DSAP/SSAP      ESCNE.w $0300,SNAPUnknownType                     ;check CTL field      ESCNE.w $0000,SNAPUnknownType      ESCNE.w $0800,SNAPUnknownProtocol                     ;check protocol type field    ; It's IP over SNAP    BdgSNAPIP:      CLOAD 5 ;assume IP header length is 5      ESCNE.w $4500,BdgSNAPIP.sub.-- withOpts                     ;check IP header      SKIP.w  ;skip length      SKIP.w  ;skip identification      SKIP.w  ;skip offset      ESCLE.b $01,BdgSNAPIP.sub.-- TTLExpired                     ;check TTL      SKIP.b  ;skip protocol      SKIP.w  ;skip checksum      MOVE  (IP)+,X              ;read NLSA      MOVE  R12(X),X              ;shift first nibble to bottom      SWITCH  ;check IP Class      BRA.u   BdgSNAPIPClassA                     ;0xxx = Class A address      BRA.u   BdgSNAPIPClassA      BRA.u   BdgSNAPIPClassA      BRA.u   BdgSNAPIPClassA      BRA.u   BdgSNAPIPClassA      BRA.u   BdgSNAPIPClassA      BRA.u   BdgSNAPIPClassA      BRA.u   BdgSNAPIPClassB                     ;10xx = Class B address      BRA.u   BdgSNAPIPClassB      BRA.u   BdgSNAPIPClassB      BRA.u   BdgSNAPIPClassB      BRA.u   BdgSNAPIPClassC                     ;110x = Class C address      BRA.u   BdgSNAPIPClassC      BRA.u   BdgSNAPIPClassD                     ;1110 = Class D address      BRA.u   BdgSNAPIPClassE                     ;1111 = Class E address (future)      BRA.u   BdgSNAPIPClassA                     ;0xxx = Class A Address    BdgSNAPIPClassA:      OR      X,$FF00,X                     ;check if broadcast      BXNE    $FFFF,BdgSNAPIP.sub.-- NLSARealign      MOVE    (IP)+,X                     ;check lower address word      BXEQ    $FFFF,BdgSNAPIP.sub.-- NLSAInvalid                     ;all ones host address      BRA.u   BdgSNAPIP.sub.-- NLSAValid                     ;broadcast SA is not allowed    BdgSNAPIP.sub.-- NLSARealign:      SKIP.w      BRA.u   BdgSNAPIP.sub.-- NLSAValid    BdgSNAPIPClassB:      MOVE    (IP)+,X                     ;check lower address word      BXNE    $FFFF,BdgSNAPIP.sub.-- NLSAValid      BRA.u   BdgSNAPIP.sub.-- NLSAValid    BdgSNAPIPClassC:      MOVE    (IP)+,X                     ;check lower address byte      OR      X,$FF00,X                     ;check if broadcast      BXEQ    $FFFF,BdgSNAPIP.sub.-- NLSAInvalid      BRA.u   BdgSNAPIP.sub.-- NLSAValid    BdgSNAPIPClassD:      SKIP.w      BRA.u   BdgSNAPIP.sub.-- NLSAValid    BdgSNAPIP.sub.-- NLSAInvalid      SWAIT   ;clean up after SALE and DALE      DWAIT      OR      XP,CMD.sub.-- DISCARD | CMD.sub.-- UNICAST,Y                     ;Load command Word      MOVEF   Y, FIRST                     ;Send Command Word      MOVEF   NULL.sub.-- CI                     ;Send CI Index      MOVEF   PORT.sub.-- CP                     ;Dest Port is CP      MOVEF   RSN.sub.-- FRC.sub.-- MAC.sub.-- SRC.sub.-- INVALID                     ;Send Reason      STOP    BdgSNAPIP.sub.-- NLSAValid:      SKIP.w  ;skip NLDA      SKIP.w      BCSERR BDG.sub.-- SNAPIP.sub.-- CSError      RSEL    LP1    ;Store source SIB pointer in LP1      SWAIT      SMOVE   Y      ;Y contains SALE result      MOVE    Y,LP,LP2                     ;LF1 points to Source Addr SIB                     ;Store dest SIB pointer in LP2      BYNZ    BDG.sub.-- SrcHit    BDG.sub.-- SrcMiss:              ;*** Source Cache Miss ***      OR      XP,CMD.sub.-- FWDCP | CMD.sub.-- UNICAST,Y                     ;Load command Word                     ;Default MAC Ethernet Type                     ;Detault Low priority      MOVEF   Y, FIRST                     ;Send Command Word      MOVEF   NULL.sub.-- CI                     ;Send CI Index      MOVEF   PORT.sub.-- CP                     ;Dest Port is CP      MOVEF   RSN.sub.-- FRC.sub.-- MAC.sub.-- SRC.sub.-- MISS                     ;Send Reason      STOP    ;Done|||    BDG.sub.-- SNAPIP.sub.-- CSError:      OR      XP,CMD.sub.-- DISCARD | CMD.sub.-- UNICAST,Y                     ;Load command Word      MOVEF   Y, FIRST                     ;Send Command Word      MOVEF   NULL.sub.-- CI                     ;Send CI Index      MOVEF   PORT.sub.-- CP                     ;Dest Port is CP      MOVEF   RSN.sub.-- FRC.sub.-- MAC.sub.-- CSERR                     ;Send Reason      STOP    BDG.sub.-- SrcHit:      DWAIT      DMOVE   Y      ;Get DALE result      MOVE    Y,LP,LP1                     ;point to source SIB      BYNZ    BDG.sub.-- CheckSrcPort                     ;and check source port    BDG.sub.-- DestMiss:              ;*** Destination Cache Miss ***      OR      XP,CMD.sub.-- FWDCP | CMD.sub.-- UNICAST,Y                     ;Load command Word                     ;Default MAC Ethernet Type                     ;Default Low priority      MOVEF   Y, FIRST                     ;Send Command Word      MOVEF   NULL.sub.-- CI                     ;Send CI Index      MOVEF   PORT.sub.-- CP                     ;Dest Port is CP      MOVEF   RSN.sub.-- FRC.sub.-- MAC.sub.-- DST.sub.-- MISS                     ;Send Reason      STOP    ;Done|||    BDG.sub.-- CheckSrcPort:      GET     SIB.sub.-- MAC.sub.-- PORTSET(LP)                     ;Compare portsets in LP => Src SIB      AND     S,PSET(X),Y                     ;Y = src addr bit AND src port bit      BYNZ    BDG.sub.-- CheckDestArea                     ;source moved if bits don't match    BDG.sub.-- SrcMove:              ;*** Source Moved ***      OR      XP,CMD.sub.-- FWDCP | CMD.sub.-- UNICAST,Y                     ;Load command Word                     ;Default MAC Ethernet Type                     ;Default Low priority      MOVEF   Y, FIRST                     ;Send Command Word      MOVEF   NULL.sub.-- CI                     ;Send CI Index      MOVEF   PORT.sub.-- CP                     ;Dest Port is CP      MOVEF   RSN.sub.-- FRC.sub.-- SRC.sub.-- MOVED                     ;Send Reason      STOP    ;Done|||    BDG.sub.-- CheckDestArea:      RSEL    LP2    ;point to dest SIB      GET     SIB.sub.-- PROTO.sub.-- AREA.sub.-- 1(LP)                     ;get IP Dest Area      AND     S,MASK.sub.-- AREA,Y;Mask off top 4 bits      BYNZ    BDG.sub.-- CheckSrcArea    BDG.sub.-- DestAreaInvalid:              ;*** Destination Area Invalid ***      LD      X      OR      X,CMD.sub.-- DISCARD | CMD.sub.-- UNICAST,Y                     ;Load command Word    ;Default MAC Ethernet Type    ;Default Low priority    ;Default Multicast      MOVEF   Y, FIRST                     ;Send Command Word      MOVEF   NULL.sub.-- CI                     ;Send CI Index      MOVEF   PORT.sub.-- CP                     ;Dest Port is CP      MOVEF   RSN.sub.-- DRC.sub.-- DST.sub.-- AREA.sub.-- INV                     ;Send Reason      STOP    ;Done|||    BDG.sub.-- CheckSrcArea:      RSEL    LP1    ;get ready for Source Addr check      GET     SIB.sub.-- PROTO.sub.-- AREA.sub.-- 1(LP)      OR      S,SIB.sub.-- AREA.sub.-- PROTO.sub.-- ACTIVE,X                     ;set PA bit in SIB.sub.-- IPAREA      MOVE    X,SIB.sub.-- PROTO.sub.-- AREA.sub.-- 1(LP)                     ;modify      AND     X,MASK.sub.-- AREA, X                     ;Mask off top 4 bits      XOR     X,Y,Y,LP2                     ;check against Dest Area    ;switch to LP2 (Dest SIB)      BYZ     BDG.sub.-- CheckDestPort    BDG.sub.-- SrcAreaInvalid:              ;*** Source Area Invalid ***      OR      XP,CMD.sub.-- DISCARD | CMD.sub.-- UNICAST,Y                     ;Load command Word    ;Default MAC Ethernet Type    ;Default Low priority    ;Default Multicast      MOVEF   Y, FIRST                     ;Send Command Word      MOVEF   NULL.sub.-- CI                     ;Send CI Index      MOVEF   PORT.sub.-- CP                     ;Dest Port is CP      MOVEF   RSN.sub.-- DRC.sub.-- SRC.sub.-- AREA.sub.-- INV                     ;Send Reason      STOP    ;Done|||    BDG.sub.-- CheckDestPort:      ;X0, LP2 are default XP, LP      LD      X      ;restore PSW      GET     SIB.sub.-- MAC.sub.-- PORTSET(LP)                     ;S = dest address portset      AND     S, PSET(X),Y                     ;compare against source port portset      BYZ     BDG.sub.-- OK    BDG.sub.-- SamePort:              ;*** Src Port = Dest Port ***      OR      XP,CMD.sub.-- DISCARD | CMD.sub.-- UNICAST,Y                     ;Load command Word    ;Default MAC Ethernet Type    ;Default Low priority      MOVEF   Y, FIRST                     ;Send Command Word      MOVEF   NULL.sub.-- CI                     ;Send CI Index      MOVEF   PORT.sub.-- NULL                     ;Dest Port is NULL      MOVEF   RSN.sub.-- DRC.sub.-- DST.sub.-- SAME                     ;Send Reason      STOP    ;Done |||    BDG.sub.-- OK:              ;*** Bridge-router ***      OR      XP,CMD.sub.-- BRIDGE-ROUTER | CMD.sub.-- UNICAST,Y                     ;Load command Word    ;Default MAC Ethernet Type    ;Default Low priority      MOVEF   Y, FIRST                     ;Send Command Word      MOVEF   SIB.sub.-- MAC.sub.-- CI(LP)                     ;Send CI Index from dst SIB      MOVEF   SIB.sub.-- MAC.sub.-- PORTSET(LP)                     ;Dest Port is determined from dst SIB      MOVEF   SIB.sub.-- MAC.sub.-- MACINDEX(LP)                     ;Get MAC Index from dst SIB      STOP    ;Done|||    __________________________________________________________________________

The described look-up engine is capable of performing bridge-router andmost network layer look-ups in less than 5.6 μs (1/178,000) with tominimum RAM requirements and cost and maximizes flexibility for futureadditions/corrections without hardware changes.

The intended application of the look-up engine is high performance LANsystems and other packet-based devices.

    ______________________________________    GLOSSARY    ______________________________________    BRIDGE-ROUTER               A LAN bridging-routing device, with 12 ethernet               ports and 1 ATM port.    ATM        Asynchronous Transfer Mode. A cell relay               standard.    ABS        Address/Broadcast Server A component of a Route               Server that handles address resolution and               broadcast traffic.    AXE        A Transfer Engine    DA         Destination Address. The MAC address of the               intended destination of a MAC frame.    DALE       Destination Address Look-up Engine. The LUE               component that generally searches through a table               of MAC layer destination addresses.    CI         Connection Identifier. A number internally used               to indicate a particular connection.    IP         Internet Protocol A popular network layer               protocol used by the Internet community.    IPX        Internet Packet Exchange A Novell developed               network layer protocol.    LEC        Look-up Engine Controller. The LUE component               that executes microcode.    LUE        Look-up Engine.    MAC        Medium Access Control. A term commonly               encountered in IEEE 802 standards generally               referring to how a particular medium (ie.               Ethernet) is used. "MAC address" is commonly               used to refer to the globally unique 48 bit address               given to all interface cards adhering somewhat to               the IEEE 802 standards.    RS         Route Server.    SA         Source Address. The MAC address of the originator               of a MAC frame.    SALE       Source Address Look-up Engine. The LUE               component that generally searches through a table of               MAC layer source addresses.    SIB        Station Information Block. The data structure in               the LUE that holds relevant information about an               endstation.    CAM        Content Addressable Memory.    VPI        Virtual Path Identifier    VCI        Virtual Channel Identifier    Control Processor               The processor in the Bridge-router that handles               management functions    ______________________________________

We claim:
 1. An arrangement for parsing packets in a packet-baseddigital communications network, said packets including packet headersdivided into fields having values representing information pertaining tothe packet, said arrangement comprising:a) an input memory for receivingfields from said packet headers of incoming packets; and (b) a look-upengine for retrieving stored information appropriate to a received fieldvalue, said look-up engine including: (i) at least one memory storinginformation related to possible values of said fields in a hierarchicaltree structure and associated with a respective field of packet headers;(ii) a memory controller associated with each said memory storinginformation related to possible values of said fields for controllingthe operation thereof to retrieve said stored information therefrom; and(iii) a microcode controller for parsing a remaining portion of thepacket header while said stored information is retrieved and controllingthe overall operation of said look-up engine.
 2. An arrangement asclaimed in claim 1, wherein said memory controller associated with eachsaid memory compares, at each decision point on the tree structure, thecurrent field with a stored value or range, and moves to the nextdecision point by moving a pointer for the current field and branchingto new code if said comparison results in a first logical condition, andif said comparison results in a second logical condition the currentfield is compared to a different value or range, and so on until saidcomparison results in said first logical condition.
 3. An arrangement asclaimed in claim 1, wherein said controller associated with each saidmemory compares values based on successive nibbles of a field value insaid memory with stored values to locate the related information.
 4. Anarrangement as claimed in claim 3, wherein said memory controllerassociated with each said memory concatenates a first nibble of anincoming field value with a root pointer to obtain an index to a rootpointer array, retrieves a word at a location identified by said index,concatenates the next nibble with the retrieved word to form the nextpointer and so on until said related information is retrieved.
 5. Anarrangement as claimed in claim 1, wherein said at least one memory is arandom access memory (RAM).
 6. An arrangement as claimed in claim 1,wherein one of said fields comprises a destination address and saidrelated information comprises the path data associated with saidrespective destination addresses.
 7. An arrangement as claimed in claim1, wherein a plurality of said memories storing information related topossible values of said fields in a hierarchical tree structure operatein parallel and are associated with respective fields of said packetheaders.
 8. An arrangement as claimed in claim 7, wherein each saidmemory is a random access memory (RAM).
 9. An arrangement as claimed inclaim 7, wherein one of said fields comprises a destination address andsaid related information comprises the path data associated with saiddestination address, and another of said fields comprises a sourceaddress, and said look-up engine also locates path data associated withthe source in parallel with the location of the path data associatedwith the destination address.
 10. An arrangement for parsing packets ina packet-based digital communications network, said packets includingpacket headers divided into fields having values representinginformation pertaining to the packet, said arrangement comprising:(a) aninput memory for receiving fields from said packet headers of incomingpackets; and (b) a look-up engine for retrieving stored informationappropriate to a received field value, said look-up engine including:(i) a plurality of memories storing information related to possiblevalues of said fields in a hierarchical tree structure and operating inparallel, said memories being associated with respective fields of saidpacket headers; (ii) a main controller controlling overall operation ofthe look-up engine; and (iii) a memory controller associated with eachsaid respective memory for controlling the operation thereof to retrievesaid stored information therefrom.
 11. An arrangement as claimed inclaim 10, wherein said main controller is a microcode.
 12. Anarrangement as claimed in claim 11, wherein said microcode controllercomprises an interface memory for receiving headers of incoming packets,a station information block memory for storing information pertaining toendstations, a microcode memory storing microcode instructions, andlogic circuitry for implementing said microcode instructions.
 13. Anarrangement as claimed in claim 11, wherein said microcode controllerparses the remainder of the packet header using a specific instructionset while said information is retrieved from said plurality of memories.14. An arrangement as claimed in claim 13, wherein said microcodecontroller comprises separate buses for instructions and data.
 15. Anarrangement as claimed in claim 14, wherein said microcode controller isarranged to implement optimized instructions that perform bit levellogical comparisons and conditional branches within the same cycle andother instructions tailored to retrieving date from nibble-indexed datastructures.
 16. An arrangement as claimed in claim 15, wherein saidmicrocode controller is implemented as an ASIC processor.
 17. Anarrangement for parsing packets in a packet-based digital communicationsnetwork, said packets including packet headers including destination andsource address fields, said arrangement comprising:(a) an input memoryfor receiving fields from said packet headers of incoming packets; and(b) a look-up engine for retrieving stored information appropriate to areceived field value, said look-up engine including: (i) a sourceaddress look-up engine including a memory storing information related topossible values of said source address field in a hierarchical treestructure; (ii) a memory controller associated with said source look-upengine for controlling the operation thereof to retrieve storedinformation therefrom; (iii) a destination address look-up engineincluding a memory storing information related to possible values ofsaid destination address field in a hierarchical tree structure; (iv) amemory controller associated with said destination look-up engine forcontrolling the operation thereof to retrieve stored informationtherefrom; (v) a processor controlling overall operation of said sourceand destination address look-up engines, said source and destinationaddress look-up engines and said processor operating in parallel.
 18. Anarrangement as claimed in claim 17, wherein said processor is amicrocode controller.
 19. An arrangement as claimed in claim 18, whereinsaid memory controllers compare, at each decision point on the treestructure, the current field with a stored value or range, and move tothe next decision point by moving a pointer for the current field andbranching to new code if said comparison results in a first logicalcondition, and if said comparison results in a second logical condition,the current field is compared to a different value or range, and so onuntil said comparison results in said first logical condition.
 20. Anarrangement for parsing packets in a packet-based digital communicationsnetwork, said packets including packet headers including destination andsource address fields, said arrangement comprising:(a) an input memoryfor receiving fields from said packet headers of incoming packets; and(b) a look-up engine for retrieving stored information appropriate to areceived field value, said look-up engine including: (i) a sourceaddress look-up engine including a memory storing information related topossible values of said source field in a hierarchical tree structure;(ii) a memory controller associated with said source look-up engine forcontrolling the operation thereof to retrieve stored informationtherefrom; (iii) a destination address look-up engine including a memorystoring information related to possible values of said destination fieldin a hierarchical tree structure and an associated memory controller;(iv) a memory controller associated with said destination look-up enginefor controlling the operation thereof to retrieve stored informationtherefrom; and iii) a microcode processor controlling overall operationof said source and destination address look-up engine, said source anddestination address look-up engines and said processor operating inparallel, and said microcode processor being arranged to parseadditional fields in said packet header while said source anddestination address look-up engines retrieve said related information.21. An arrangement as claimed in claim 20 wherein said microcodeprocessor comprises an interface memory for receiving said incomingpackets, a station information block memory for storing informationpertaining to endstations, a microcode memory storing microcodeinstructions, and logic circuitry for implementing said instructions.22. A method of parsing packets in a packet-based digital communicationsnetwork, said packets including packet headers divided into fieldshaving values representing information pertaining to the packet,comprising the steps of:(a) receiving fields of packet headers fromincoming packets in an input memory; (b) retrieving stored informationappropriate to a received field value by performing a tree search in alook-up engine having at least one memory storing information related topossible values of said fields in a hierarchical tree structure andassociated with a respective field of packet headers, said at least onememory being controlled by a memory controller associated therewith toretrieve said stored information therefrom; and (c) parsing a remainingportion of the packet header while said stored information is beingretrieved from said at least one memory with a main controller, whichmain controller also controls the overall operation of said look-upengine.
 23. A method as claimed in claim 22, wherein at each decisionpoint in the tree search, in retrieving said information the currentfield is compared with a stored value or range, a pointer for thecurrent field is moved and branched to new code if said comparisonresults in a first logical condition, and if said comparison results ina second logical condition, the current field is compared to a differentvalue or range, and so on until said comparison results in said firstlogical condition.
 24. A method as claimed in claim 22, wherein valuesbased on successive nibbles of a field value are compared with storedvalues to locate the related information.
 25. A method as claimed inclaim 24, wherein a first nibble of an incoming field value isconcatenated with a root pointer to obtain an index to a root pointerarray, a word at a location identified by said index is retrieved, thenext nibble is concatenated with the retrieved word to form the nextpointer and so on until said related information is retrieved.
 26. Amethod as claimed in claim 22, wherein information related to aplurality of fields is retrieved in parallel.
 27. A method as claimed inclaim 26, wherein one of said fields comprises a destination address andsaid related information comprises the path data associated with saidrespective destination address, and another of said fields comprises asource address and said related information comprises the path dataassociated with said source address.
 28. A method of parsing packets ina packet-based digital communications network, said packets includingpacket headers divided into fields having values representinginformation pertaining to a packet, comprising the steps of:(a) storingin memory information related to possible values of said fields in ahierarchical tree structure; (b) receiving a plurality fields from saidpacket headers of incoming packets, one of said fields being adestination address and said related information therefor comprisingpath data associated with said respective destination address, andanother of said fields being a source address and said relatedinformation therefor comprising path data associated with said sourceaddress; (c) retrieving in parallel said stored information appropriateto received field values by performing a tree search under the controlof a microcode controller; and (d) parsing a remaining portion of thepacket header using a specific instruction set while said relatedinformation is retrieved.
 29. An arrangement as claimed in claim 1,wherein said at least one memory provides table look-ups using nibbleindexing for variable portions of the packet header and said microcodecontroller employs bit pattern recognition on fixed portions of thepacket header for network layer protocol determination.